RISC-V is in a paradigm shift of the industry architecture as it is being developed and refined to leave the academic instruction set behind and evolve into a commercial-grade and proven CPU ecosystem. What started as a barebones-style of embedded controllers has now become a full performance range with ultra-low power microcontroller-style designs congruent with Arm Cortex-M0 to high-performance application-class processors congruent with Cortex-A55. This development has made RISC-V IP cores a strategic decision of companies who would like to be open, scale, secure, and architecturally independent over the long term.
The modern development of products is no longer able to be single handed. Smart IoT nodes must be power efficient to a fault, industrial controllers must be deterministic real time, automotive systems must be functionally safe and AI edge platforms must be scalable with computers including vector and cryptographic accelerators. An integrated RISC-V IP stack between M0 and A55-class performance allows silicon designers to use a single ISA, and customize microarchitectures to each application domain.
This article discusses the full range of the performance of RISC-V IP cores, how architecture design choices can be scaled between entry-level MCUs and advanced 64-bit application processors, and how production-proven RISC-V CPU IP can be implemented on consumer, industrial, automotive, and AI edge systems.
The current RISC-V IP cores are not experimental anymore. RV32 and RV64 Instruction sets are now being implemented on silicon with both instruction sets providing performance equivalents to M0 to A55-class designs. Such cores combine with innovative characteristics like DSP extensions, floating point units, vector crypto acceleration, superscalar pipelines, and functional safety systems meeting ASIL-B and ASIL-D requirements.
This breadth enables system architects to share software, toolchains and verification flows across levels of products. Regardless of the markets of smart IoT devices, consumer electronics, industrial automation, automotive ECUs, or AI edge platforms, RISC-V IP cores provide a standardized architecture with a wide range of customization of the underlying core microarchitecture to bus interfaces.
M0 and A55 are commonly used as points of reference of performance and not as a point of comparison. M0-class processors, which are the smallest power area microcontroller designs, are designed to perform simple control. Instead, A55-class processors are application-class CPUs that can support rich operating systems, virtual memory, and high-level workloads.
This spectrum is implemented in the RISC-V ecosystem with variations in pipeline depth, issue width, memory hierarchy, and instruction set extensions along with system-level features. One of the strongest opportunities of RISC-V is the ability to scale within the same ISA.
The portfolio is based on general-purpose RISC-V-based IP cores, including all the way up to high-performance compute engines. These cores are power, performance, and area optimized so that designers can choose the optimal balance that can be used in their application.
The TGE100 is a 32-bit two-stage CPU with the RV32EMCZc instruction set. It is optimized to be in the M0-class, with focus on area and extreme power usage. It is an ideal core that can support deeply embedded control applications, simple IoT devices, and always-on subsystems in which cost and energy efficiency are important.
The TGE302 is based on the entry-level design that has three-stage pipeline and RV32 EMZc/C support. It has similar features like M0+ performance which includes TIM, CLIC, and AHB interfaces hence is the best to use in more responsive control applications but still with high power efficiency.
The TGE310 is aimed at M3-class performance and uses a three-stage pipeline to use RV32 IMAC. It has up to 7 computational units and system integration of industrial controllers and connected devices using TIM, PMP, CLIC, and AHB.
The TGE315 provides M33 performance in a three stage RV32 IMAC/Zc(B)(F) pipeline. It is an amalgamation of FPU support, trusted execution environments, ECC, AXI interfaces, and CLIC. This provides it with a good fit in secure embedded systems where both performance and protection is needed like smart metering and industrial IoT.
The TGE320 offers M4-class performance on a three-stage RV32 IMAC(B) (F)(P) architecture. This core can be used in consumer and industrial electronics by means of DSP extensions, floating-point support, trace capability, CLIC, and AHB-Lite interfaces.
At the very highest of the 32-bit general-purpose hierarchy, the TGE330 offers an impressive M7-like performance with a six-stage, dual issue RV32 IMAC/Zc(B)(FD)(P)(Zicond) based architecture. It can support applications at the high end of MCUs that can be run on DSP and AXI with the requirement that it does not need to go to 64-bit architecture.
TGS500 is a 64 bit, two issue, RVA23-compliant CPU with a 9-pipeline. It has comparable features with Cortex-A55, adding both a vector and cryptography accelerator, which allows it to provide complex workloads, secure processing, and AI edge inference. This core is compatible with Linux capable systems, gateways and high performance embedded boards.
Intelligent embedded RISC-V IP cores are secure and have added enhanced safety and reliability capabilities to the general-purpose portfolio. The cores are automotive and industrial-enabled and functional safety, fault-tolerance and certification-ready are required.
TAE302 is a three-stage ASIL-B compliant, 32-bit core, with Zc support, ECC, stack pointer monitoring and CLIC. Similar to M0+ performance, it is designed to be used in safety-critical control applications in automobile and industrial settings.
The TAE320 is based on a three-stage lockstep pipeline with DSP support and features M4-like performance. It is a safety MCU that is developed to give deterministic implementation to real-time control systems.
The TAE330 is safety-scaled to ASIL-D but still has M7-class performance. It uses a six-stage, in-order, superscalar pipeline, which implements RV32 IMAC(B)(FD)(P)(K)(Zicond), which can be used to provide high-performance processing in safety-critical applications.
The TAE500 has a six-stage in-order pipeline superscalar and is ASIL-B certified. It uses RV32 IMAC(B)(FDZfh)(P)(Zicond) to achieve R5-class performance that can be used in complex automotive controllers.
The TAE520, at the highest end of the 32-bit safety range, is ASIL-D compliant and has a 6-stage superscalar pipeline. Similar to R52 performance, it incorporates advanced safety systems to mission-critical automotive and industrial systems.
The TAS500 is a 64-bit, dual-issue, and nine-stage CPU with 9 stages of ASIL-B compliance and performance at A55 speed. It combines the TEE, ECC, MMU, SMP support, and AXI interfaces and thus it is applicable to the automotive and industrial safety-capable application processors.
Besides general-purpose design and safety-oriented design, specific RISC-V IP cores serve specialized tasks like AI acceleration, neural processing, and information security. These cores broaden the performance range with domain optimizations.
TDS516A is a 64 bit, two-issue, eight-stage superscalar, in-order CPU, that supports RVA23. Similar to A55 performance, it includes the use of a vector crypto acceleration, which can be used to support secure and high throughput processing to AI edge and secure computing environments.
The TDS350N is a 64-bit, two-issue, eight-stage in-order, superscalar based on RVV 1.0 CPU. It is targeted at workloads in the AI and NPU-class range, has A55-like performance, and supports even better vector processing.
They are the TDE000S, a 32-bit, dual-stage pipeline core, and implementation of RV32 EMC/Zc. It is similar in performance to SC000-class performance and is used in information security applications where simplicity, determinism, and safe execution are important issues.
Flexibility is one of the characteristics of this RISC-V IP portfolio. The architecture of the core, the depth of the pipeline, the instruction extensions, the memory interfaces as well as the safety features can be customized to meet the needs of a particular project. This personalization will guarantee the highest power, performance and area as well as software compatibility along the range of performance of M0-A55.
The RISC-V ecosystem is mature and scalable as evidenced by the progress of RISC-V IP cores starting with the M0-class microcontrollers to A55-class application processors. Having been implemented in production across 32-bit and 64-bit architectures, including built-in safety and security capabilities and hardware-based support of AI and cryptography, the RISC-V can now provide a full IP of a CPU core in the modern silicon design.
With a single RISC-V portfolio, organizations will be able to both simplify their development and minimize vendor lock-in, as well as future-proof their products in the IoT, consumer, industrial, automotive, and AI edge markets. Nano-low-power embedded control up to application processing on the high-performance band, the RISC-V performance range is no longer a claim feature, but an actually deployed silicon implementation.
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